This invention relates to parallel type electronic digital arithmetic devices, namely, parallel binary adders and parallel binary subtractors, for adding or subtracting two multidigit numbers to produce a resultant multidigit number representing the sum or difference of such two numbers. While not limited thereto, the present invention is particularly useful in the arithmetic and logic sections of relatively large scale digital computers and digital data processing machines.
Many and various types of electronic digital adders and subtractors have been heretofore used, and most of them operate with varying degrees of success in terms of speed and performance. Generally, such digital adders and subtractors have been used in digital computers and digital data processing machines wherein the adder or subtractor is but one of many functional components or elements making up the computer or machine. In such cases, it is the speed and performance of the machine as a whole which is the more important consideration. With this in mind, it is a primary purpose of the present invention to provide a new and improved high speed digital arithmetic device (adder or subtractor) having an increased degree of flexibility, which flexibility can be used to considerably improve the effective speed and performance of a digital computer or digital data processing machine.
One direction of continual emphasis in the computer industry is to build better and better machines capable of processing greater amounts of data in shorter lengths of time. One technique used in an effort to increase the speed of a computer is to increase the width of the data flow or, in other words, to increase the number of data bits which can be handled simultaneously by the functional elements and interconnecting data buses. The use of relatively wide data flow widths, however, gives rise to other problems which tend to reduce the effective speed of the machine. If, for example, an adder or subtractor having a relatively wide data flow width is used and it is desired to add or subtract data fields or data items of less than the full adder or subtractor width, then in many cases such data fields must be shifted all the way to the right or, in other words, right justified before they enter the adder or subtractor. This right justification takes time and is particularly objectionable where the data field is relatively small and located at or near the leftmost side of a relatively wide data flow. The present invention, however, enables the realization of an adder or subtractor of relatively wide data flow width which can be operated so as to eliminate the need to right justify data items of less than the full adder or subtractor width. This considerably increases the speed of performing arithmetic operations on such data items.
Another criticism with respect to relatively wide adders or subtractors is that when working with lesser width data fields, a goodly portion of the adder or subtractor may, in effect, remain idle. A further increase in the data processing speed could be obtained by simultaneously using such idle portion of the adder or subtractor to perform a second and separate arithmetic or logical function of either the same or a different type. For example, when using relatively short data fields, it would frequently be desirable to simultaneously perform two or three separate and different mathematical operations on different sets of data with one and the same adder or subtractor. This desirable result can also be accomplished by proper operation of an adder or subtractor constructed in accordance with the present invention.
An arithmetic device (adder or subtractor) constructed in accordance with the present invention provides a high degree of flexibility. It can be operated as one real wide arithmetic device or it can be operated as two or three independent arithmetic devices of lesser width. And the widths and locations of the individual arithmetic zones can be varied. Also, the arithmetic device can be operated as a single zone device of variable width or variable zone location or both. And, most importantly, the change from one operating condition to another can be accomplished quickly and automatically by the control words or microcode contained in the control storage portion of a microprogrammed computer data processor or by the hardware in the control section if the computer or data processor is not of the microprogrammed type. Thus, the arithmetic device can be switched from one condition to another to from one machine cycle or control word to the next.
For a better understanding of the present invention, together with other and further advantages and features thereof, reference is made to the following description taken in connection with the accompanying drawings, the scope of the invention being pointed out in the appended claims.